1. Field of the Invention
The invention relates in general to a memory field, and more particularly to a memory controller and an associated signal generating method.
2. Description of the Related Art
A memory controller, generally connected to a memory module, writes data into the memory module or reads data from the memory module. One of the most common memory modules is a double data rate (DDR) memory module.
FIG. 1A and FIG. 1B show a schematic diagram of a connection relationship and an eye diagram of control signals between a memory controller and a memory module, respectively. A memory controller 100 and a DDR memory module 110 are disposed on a printed circuit board (PCB). Control signals include a clock signal CLK1, address signals A[15:0], a command signal CMD, and bank control signals BANK[2:0]. The command signal CMD includes a write enable signal WE, a row address strobe RAS, and a column address strobe CAS. The bank control signals BANK[2:0] are respectively present at 3 pins, and the address signals A[15:0] are respectively present at 16 pins.
The memory controller 100 utilizes the control signals to control and access the DDR memory module 110, e.g., to read and write data. The DDR memory module 110 latches data in the address signals A[15:0], the command signal CMD and the bank control signals BANK[2:0] according to a signal edge (e.g., a rising edge or a falling edge) of the clock signal CLK1. Thus, the memory controller 100 needs to appropriately adjust the phase of the clock signal CLK1, so that the DDR memory module 100 is allowed to successfully latch the data in all of the control signals according to the signal edge of the clock signal CLK1. For illustration purposes, in the example in the description below, the rising edge of the clock signal CLK1 is utilized to latch the signals.
As shown in FIG. 1B, a period of the clock signal CLK1 is T, and periods of the address signals A[15:0], the command signal CMD and the bank control signals BANK[2:0] are also T. However, as driving capabilities of the control signals are different, latching intervals (or referred to as effective data ranges) of the control signals are smaller than T. Therefore, to prevent the control signals from latching these control signals outside the latching intervals and thus from causing errors, the memory controller 100 needs to adjust the rising edge of the clock signal CLK1 to within the latching intervals of these control signals.
As shown in FIG. 1B, the rising edge of the clock signal CLK1 is adjusted to the latching interval Eye_cmd of the command signal CMD, the latching interval Eye_bank of the bank control signals BANK[2:0], and the latching interval Eye_addr of the address signals A[15:0]. It is apparent that the latching intervals of the above signals are all smaller than T. More particularly, having a large number of signals, the address signals A[15:0] has the smallest latching interval Eye_addr.
As the access speed of dynamic random access memories (DRAMs) continue to increase, DDR2 modules have evolved to DDR3 and DDR4 modules. However, with the increasing speed of memory modules, signal quality is significantly lowered. On further account of variations of PCBs and different pins of the memory modules of different specifications, slight differences may exist in the time that control signals need to travel from the memory controller to the memory module, and the rising time and falling time when signals are changed may be different. As a result, the latching intervals of the control signals become even smaller.
FIG. 2A and FIG. 2B show a schematic diagram of a connection relationship and an eye diagram of control signals between a memory controller and two memory modules, respectively. When controlling two DDR memory modules 210 and 220 by a memory controller 200, a first clock signal CLK1 connects to the first DDR memory module 210, and a second clock signal CLK2 connects to the second DDR memory module 220. Further, the two DDR memory modules 210 and 220 share address signals A[15:0], a command signal CMD, and bank control signals BANK[2:0]. That is, the first DDR memory module 210 latches the data in the address signals A[15:0], the command signal CMD and the bank control signals A[15:0] according to the first clock signal CLK1; the second DDR memory module 220 latches the data in the address signals A[15:0], the command signal CMD and the bank control signals BANK[2:0] according to the second clock signal CLK2.
The memory controller 200 is required to drive a pin count that is twice of that of the memory in FIG. 1A. In addition, considering variations of PCBs and different pins of the two DRAMs, the quality of the signals is further deteriorated. Such signal deterioration is particularly severe for the address signals A[15:0]. Compared to FIG. 1B, the latching intervals in FIG. 2B are even smaller, and particularly the latching interval Eye_addr of the address signals A[15:0] is extremely small. That is, with the extremely small latching interval Eye_addr of the address signals A[15:0], it is made even more challenging for the memory controller 200 to make adjustment to provide appropriate phases for the clock signals CLK1 and CLK2 that allow the two DDR memory modules 210 and 220 to successfully latch the signals.
Under high-speed requirements, the quality of all of the signals cannot be easily qualified. Therefore, there is a need for a solution that overcomes the above issues.